1. Technical Field
Embodiments described herein relate to wired-line transmitters. More particularly, the embodiments described herein relate to systems and methods for mitigating power supply disturbances in wired-line transmitters.
2. Description of Related Art
Modern integrated wired-line transmitters for semiconductor devices (e.g., SoC devices) may achieve data rates up to Gb/s (gigabytes pers second) or higher (e.g., tens of Gb/s). Wired-line transmitters may be used in cost effective mediums such as microstrip and Cat5 cable. The use of wired-line transmitters in such mediums allows high-speed chip-to-chip communications in consumer electronics. The driver of wired-line transmitters is a major implementation that may directly drive the off-chip loading. A typical embodiment of drivers of a wired-line transmitter is shown in FIG. 1. Transmitter 100 may include a number, N, of identical legs with each leg including driver 102 and termination resistor 104 (with resistance R). Transmitter 100 may include logic gate 106 driven by input signal 108 and enable signal 110 on the input of the driver system and load 112 (with loading resistance RL) on the output of the transmitter.
At Gb/s speeds, impedance control in transmitter 100 is required for maximum power delivery. Thus, the number of legs, N, and the resistance, RL, of termination resistors 104 may be chosen such that the overall impedance (R/N) matches the loading resistance (RL). The operation current may then be the supply voltage for drivers 102 (VDD) divided by twice the loading resistance (e.g., the operating current is VDD/(2 RL). 50Ω (ohm) impendance matching may be typically used, which may provide an operation current that ranges from several mA (milliamps) to tens of mA depending on the signal swings required (as determined by different standards).
During power-up, the current of transmitter 100 may jump abruptly from 0 to full current, and vice versa during power-down. Due to the parasitic behavior of a chip package and/or board routing, the chip package and/or board routing may create tens of mV (millivolts), even hundreds of mV, disturbance on the power supply. The power supply disturbance may take a considerable amount of time to die out. This disturbance may not only degrade the driver's own jitter performance but also may affect other blocks on a chip (e.g., an SoC or a system on a chip) through the power supply, which may be hazardous in SoC environments.
FIG. 2 depicts a representation of an embodiment of typical SoC configuration 200. In certain embodiments, SoC configuration 200 includes board trace & package 202 coupled to power grid 204. Several components/devices may be located inside chip boundary 206 and be coupled to power grid 204 and/or each other. Examples of components/devices in SoC configuration 200 include, but are not limited to, clock generators 208, processor 210, coprocessor 212, RAM 214, Flash 216, JTAG connector 218, digital baseband 220, analog baseband 222, first I/O 224 with transmitter 226 and receiver 228, and second I/O 230 with transmitter 232 and receiver 234.
As shown in FIG. 2, transmitter 226 of first I/O 224 may kick (disturb) the power supply in power-up or power-down as marked by disturbance 236. Disturbance 236 may propagate throughout the power network to every neighbor in the same power domain, as shown by disturbances 238. Disturbances 238 may degrade the signal integrity of other transmitters, worsen the sensitivity of receivers, deteriorate clock jitter in clock generation circuitry (e.g., clock generators 208), and/or corrupt the timing of processors (e.g., processor 210 and/or coprocessor 212). Thus, mitigation of supply disturbances (such as disturbance 236) may be essential for proper operation of SoC configuration 200.
Conventional solutions to mitigate supply disturbances (e.g., disturbance 236) may include increasing on-chip decoupling capacitance (e.g., number of decoupling capacitors), increasing the number of bumps for the supply, and/or better chip packaging. These solutions may, however, be costly and somewhat ineffective in mitigating the disturbances.